Traditionally, VLSI memories have been designed to allow quick access to, and modification of, data stored in the memories, within a single memory cycle. A corollary of that design strategy is to set a lower bound on memory cycle time for a given memory size within the limitations of a particular technology (CMOS, GaAs). A consequence of that design strategy is that increases in memory size result in a proportional increase in cycle time caused by an increased capacitance of bit lines and word lines. Thus, memory designers had to balance the benefits of greater memory size against the disadvantages of slower access time.
Efforts to increase memory size without increasing access time have led memory designers to partition a memory into small modules called "blocks" that allow shorter word lines and bit lines per block, thereby improving both access time and memory throughput. In these new designs, communication to and from the blocks of memory are established via a bus that is used to broadcast input addresses and data to all blocks, and to transmit data retrieved from a selected block to the chip output pins. Although these techniques have resulted in faster and higher throughput, the size of memories using these techniques is limited. Specifically, a point of diminishing return is reached when propagation delay through the bus (whose length increases with an increasing number of blocks) and other interconnect delays outweigh the reduced time required to access a block.